Hello, currently i am working on implementing mtime and mtimecmp registers. My design is basic 32-bit, only machine mode, 1 core (basic structure). My idea was to use MCYCLE/H`s counter but this idea died the moment i learnt what MCOUNTINHIBIT is :). So is it possible to make them both csr-s?
Hello, currently i am working on implementing mtime and mtimecmp registers. My design is basic 32-bit, only machine mode, 1 core (basic structure). My idea was to use MCYCLE/H`s counter but this idea died the moment i learnt what MCOUNTINHIBIT is :). So is it possible to make them both csr-s?
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